FPGA Series
FPGA Series: Complete Zynq Embedded System Design Practice
From architecture deep-dive to three capstone projects, covering the complete Zynq-7000 HW/SW co-design workflow. 29 hands-on articles in five progressive layers, with an open-source FPGA toolchain extension series.
One goal: build a real Zynq system on Pynq-Z2 (XC7Z020) from scratch — one that runs Linux, uses PL for hardware acceleration, and connects to networks and devices. Every step explains the "why" and documents the pitfalls. Five progressive layers: hardware foundations, Linux system, driver development, advanced features, and engineering practice. Toolchain fixed at Vivado / Vitis / PetaLinux 2023.2.
Knowledge Map & Reading Order
PS → PL → Linux → Project
Start with the Zynq path to build a complete PS/PL, AXI, Linux, driver, and project workflow. The open-source FPGA toolchain track is an independent extension you can enter afterward.
Track A · Hardware Foundations
From Zynq-7000 architecture dissection to Vivado flow, PS configuration, AXI protocol, custom IP, and complete hardware platform design. Seven articles bridging the gap from datasheet to a working .xsa file.
Dissecting the Zynq-7000 Architecture
Installing Vivado / Vitis / PetaLinux 2023.2 Without Pain
From Empty Project to Blinking LED
Clocks, DDR Timing, and MIO Mapping
Handshake, Burst Alignment, and PS-PL Bus
From AXI4-Lite Template to a Working PWM IP
IP Integrator: Block Design to .xsa Export
Track B · Linux System Layer
PetaLinux build pitfalls, FSBL-to-U-Boot boot chain, character device driver skeleton, and three paths (UIO / /dev/mem / kernel driver) to access PL from Linux. Four articles to get Linux running and controlling PL.
Track C · Driver Development
AXI DMA engine driver (measured 803 MB/s), VDMA + HDMI 1080p video pipeline, AXI-Stream high-speed ADC. Three articles to make data flow fast.
Track D · Advanced Features
Vitis HLS, PYNQ, lwIP networking, OpenAMP dual-core, secure boot, Vitis AI deployment, system reliability, mixed criticality. Nine articles covering the full range of advanced Zynq capabilities.
The Right Way to Write Hardware IPs in C
Controlling PL from Python in Jupyter
lwIP + GigE: A Working HTTP Server
Linux + Bare-Metal on Dual Cores (AMP)
FSBL Encryption, RSA Signing, and eFuse
Running Trained Models on the PL Accelerator
Watchdog, ECC Memory, and Fault Recovery
TrustZone Isolation + FreeRTOS + Linux
Track E · Engineering & Projects
Co-simulation (QEMU), Git + CI/CD engineering, Capstone audio FFT, three major projects (data acquisition / machine vision / industrial gateway), and a 29-chapter knowledge map finale.
QEMU + Vivado Co-Sim: Validate Without Hardware
Git for Vivado Projects + GitHub Actions CI
Audio Capture → Real-Time FFT → Web Spectrum
Smart Data Acquisition System
Machine Vision Platform
Industrial Communication Gateway
30-Chapter Review + Troubleshooting + Roadmap
Track F · Open-Source FPGA Toolchain
Standalone extension series: iCEstick / ECP5 / Gowin FPGA, NextPnR timing, SymbiYosys formal verification, LiteX SoC, cocotb simulation, open-source HLS, MicroLED controller prototype, and CI/CD. Ten articles taking the open-source route outside Vivado.
iCEstick: Full Open-Source Chain, LED to UART
NextPnR Constraints and Critical Path Fixing
SymbiYosys: Proving Your RTL Correct
VexRiscv CPU + DDR3 + Ethernet Full Config
Python Testbenches: Goodbye Verilog Testbench
HDMI Output + SD Card + ESP32 Co-Design
Tang Nano 9K Open-Source Full Flow
Bambu vs Vitis HLS: Free C-to-RTL
MicroLED Driver Controller: Requirements to FPGA
GitHub Actions: Auto Synthesis + Sim + Timing
Recommended Reading Order
If this is your first time through the series, follow Track A → B → C → D → E in order — each layer builds on the previous one. If you are already familiar with Linux drivers, jump directly to Track C or D for topics of interest. Track F is a standalone open-source toolchain extension that does not require a Zynq board and can be started at any time.